All fields marked * are required
ASIC Engineer – DFT / ATPG
Location: Hyderabad
Experience: 4–6 Years
Employment Type: Full-Time
Open Positions - 2
We are looking for an experienced ASIC Engineer 2 with strong hands-on expertise in DFT implementation, Scan Insertion, ATPG Pattern Generation & Validation, and RTL/Gate-Level DFT verification.
The candidate will work closely with design, verification, and DFT teams to implement and validate test structures, generate high-quality ATPG patterns, improve fault coverage, and support silicon test readiness.
4–6 years of relevant experience in ASIC DFT / Design for Test
Strong hands-on experience in Scan Insertion
Strong experience in ATPG pattern generation and validation
Experience with DFT RTL and Gate-Level implementation/verification
Strong understanding of scan chains, test modes, compression, and fault models
Experience in debugging ATPG and scan-related failures
Hands-on exposure to Siemens, Synopsys, and/or Cadence DFT tools
Good knowledge of Verilog and/or VHDL
Proficiency in scripting using TCL, Perl, and/or Python
Exposure to C/C++ for automation or validation tasks
Perform scan insertion and scan-chain implementation for ASIC/SoC designs.
Generate and validate ATPG patterns for manufacturing test.
Analyze and improve stuck-at and transition fault coverage.
Perform DFT validation at RTL and Gate-Level.
Debug scan-chain, ATPG, test-mode, and timing-related issues.
Work on DFT rule checks and resolve violations.
Support pattern simulation and gate-level verification.
Develop automation scripts using TCL, Perl, or Python.
Work with design and physical-design teams to ensure DFT implementation quality.
Support test readiness, coverage closure, and tape-out activities.
Experience with scan compression and advanced ATPG methodologies.
Exposure to MBIST / LBIST / Boundary Scan.
Experience with post-layout or timing-aware pattern validation.
Familiarity with silicon bring-up and production test flows.
Experience working on complex ASIC or SoC projects.
ATPG | Scan Insertion | DFT | Pattern Generation | Pattern Validation | RTL DFT | Gate-Level DFT | Siemens DFT Tools | Synopsys DFT Tools | Cadence DFT Tools | Verilog | VHDL | C/C++ | TCL | Perl | Python | Fault Coverage | Scan Compression
Required
Preferred
All fields marked * are required
ASIC Engineer – DFT / ATPG
Location: Hyderabad
Experience: 4–6 Years
Employment Type: Full-Time
Open Positions - 2
We are looking for an experienced ASIC Engineer 2 with strong hands-on expertise in DFT implementation, Scan Insertion, ATPG Pattern Generation & Validation, and RTL/Gate-Level DFT verification.
The candidate will work closely with design, verification, and DFT teams to implement and validate test structures, generate high-quality ATPG patterns, improve fault coverage, and support silicon test readiness.
4–6 years of relevant experience in ASIC DFT / Design for Test
Strong hands-on experience in Scan Insertion
Strong experience in ATPG pattern generation and validation
Experience with DFT RTL and Gate-Level implementation/verification
Strong understanding of scan chains, test modes, compression, and fault models
Experience in debugging ATPG and scan-related failures
Hands-on exposure to Siemens, Synopsys, and/or Cadence DFT tools
Good knowledge of Verilog and/or VHDL
Proficiency in scripting using TCL, Perl, and/or Python
Exposure to C/C++ for automation or validation tasks
Perform scan insertion and scan-chain implementation for ASIC/SoC designs.
Generate and validate ATPG patterns for manufacturing test.
Analyze and improve stuck-at and transition fault coverage.
Perform DFT validation at RTL and Gate-Level.
Debug scan-chain, ATPG, test-mode, and timing-related issues.
Work on DFT rule checks and resolve violations.
Support pattern simulation and gate-level verification.
Develop automation scripts using TCL, Perl, or Python.
Work with design and physical-design teams to ensure DFT implementation quality.
Support test readiness, coverage closure, and tape-out activities.
Experience with scan compression and advanced ATPG methodologies.
Exposure to MBIST / LBIST / Boundary Scan.
Experience with post-layout or timing-aware pattern validation.
Familiarity with silicon bring-up and production test flows.
Experience working on complex ASIC or SoC projects.
ATPG | Scan Insertion | DFT | Pattern Generation | Pattern Validation | RTL DFT | Gate-Level DFT | Siemens DFT Tools | Synopsys DFT Tools | Cadence DFT Tools | Verilog | VHDL | C/C++ | TCL | Perl | Python | Fault Coverage | Scan Compression
Required
Preferred