All fields marked * are required
Design Verification Engineer – III
Location: Noida
Experience: 8–12 Years
Employment Type: Full-Time
We are looking for an experienced Design Verification Engineer – III with strong hands-on expertise in SystemVerilog, UVM, SoC/IP/Subsystem Verification, RTL Debugging, coverage closure, formal verification, and low-power verification.
The candidate will be responsible for developing and maintaining advanced verification environments, debugging complex RTL issues, driving functional and assertion coverage, and supporting verification sign-off for SoC/IP designs.
8–12 years of relevant Design Verification / ASIC / SoC Verification experience
Strong hands-on experience with SystemVerilog and UVM
Experience in SoC, IP, and Subsystem-level verification
Strong knowledge of Verilog and/or VHDL
Hands-on experience with AXI, AHB, and AMBA protocols
Experience with ARM Core-based architectures
Strong expertise in RTL debugging and root-cause analysis
Experience in functional coverage and assertion-based verification
Hands-on exposure to formal verification
Experience with low-power verification using UPF and/or CPF
Strong experience in simulation, regression, debugging, and coverage closure
Develop and maintain reusable SystemVerilog/UVM-based verification environments.
Create testbenches, sequences, drivers, monitors, scoreboards, assertions, and coverage models.
Perform SoC/IP/Subsystem-level verification.
Validate interfaces and protocols including AXI, AHB, and AMBA.
Perform verification of ARM-based SoC architectures.
Debug RTL and simulation failures and identify root causes.
Drive functional, assertion, and code coverage closure.
Develop and execute constrained-random and directed tests.
Perform formal verification and property checking.
Validate low-power functionality using UPF/CPF, including isolation, retention, and power-state transitions.
Execute regressions, analyze failures, and improve verification quality.
Collaborate with RTL design, architecture, and verification teams.
Support verification sign-off and tape-out readiness.
SystemVerilog | UVM | SoC Verification | IP Verification | Subsystem Verification | Verilog | VHDL | AXI | AHB | AMBA | ARM Cores | RTL Debug | Functional Coverage | Assertion Coverage | Formal Verification | UPF | CPF | Low-Power Verification | Coverage Closure
Required
Preferred
All fields marked * are required
Design Verification Engineer – III
Location: Noida
Experience: 8–12 Years
Employment Type: Full-Time
We are looking for an experienced Design Verification Engineer – III with strong hands-on expertise in SystemVerilog, UVM, SoC/IP/Subsystem Verification, RTL Debugging, coverage closure, formal verification, and low-power verification.
The candidate will be responsible for developing and maintaining advanced verification environments, debugging complex RTL issues, driving functional and assertion coverage, and supporting verification sign-off for SoC/IP designs.
8–12 years of relevant Design Verification / ASIC / SoC Verification experience
Strong hands-on experience with SystemVerilog and UVM
Experience in SoC, IP, and Subsystem-level verification
Strong knowledge of Verilog and/or VHDL
Hands-on experience with AXI, AHB, and AMBA protocols
Experience with ARM Core-based architectures
Strong expertise in RTL debugging and root-cause analysis
Experience in functional coverage and assertion-based verification
Hands-on exposure to formal verification
Experience with low-power verification using UPF and/or CPF
Strong experience in simulation, regression, debugging, and coverage closure
Develop and maintain reusable SystemVerilog/UVM-based verification environments.
Create testbenches, sequences, drivers, monitors, scoreboards, assertions, and coverage models.
Perform SoC/IP/Subsystem-level verification.
Validate interfaces and protocols including AXI, AHB, and AMBA.
Perform verification of ARM-based SoC architectures.
Debug RTL and simulation failures and identify root causes.
Drive functional, assertion, and code coverage closure.
Develop and execute constrained-random and directed tests.
Perform formal verification and property checking.
Validate low-power functionality using UPF/CPF, including isolation, retention, and power-state transitions.
Execute regressions, analyze failures, and improve verification quality.
Collaborate with RTL design, architecture, and verification teams.
Support verification sign-off and tape-out readiness.
SystemVerilog | UVM | SoC Verification | IP Verification | Subsystem Verification | Verilog | VHDL | AXI | AHB | AMBA | ARM Cores | RTL Debug | Functional Coverage | Assertion Coverage | Formal Verification | UPF | CPF | Low-Power Verification | Coverage Closure
Required
Preferred