Mixed-Signal Verification Engineer – Level 4

Mixed-Signal Verification Engineer – Level 4

Location: Hyderabad / Bangalore

Experience: 6+ Years

Employment Type: Full-Time

Job Overview

We are looking for an experienced Mixed-Signal Verification Engineer with strong hands-on expertise in mixed-signal co-simulation, SystemVerilog/UVM, Verilog-AMS/RNM, behavioral modeling, and model-to-schematic verification.

The candidate will be responsible for developing and validating mixed-signal verification environments and ensuring correlation between behavioral models and transistor-level implementations.

Mandatory Skills

• 6+ years of relevant Mixed-Signal / AMS Verification experience

• Strong experience with SystemVerilog and UVM

• Hands-on experience with Verilog-AMS and/or Real Number Modeling (RNM)

• Experience in mixed-signal co-simulation

• Strong hands-on experience with Cadence Xcelium, Virtuoso, and Spectre

• Experience in behavioral model development and validation

• Strong experience in model vs schematic verification and correlation

• Experience in simulation debugging, regression, and verification closure

• Proficiency in Python, Perl, and/or TCL scripting

Key Responsibilities

• Develop and maintain mixed-signal verification environments.

• Perform analog/digital co-simulation using SystemVerilog/UVM and AMS models.

• Develop and validate Verilog-AMS/RNM behavioral models.

• Perform behavioral model vs schematic correlation.

• Debug simulation mismatches and mixed-signal integration issues.

• Develop automation scripts for simulation and regression workflows.

• Work closely with analog, RTL, modeling, and verification teams.

• Support verification planning, regression analysis, and sign-off activities.

Key Skills

Mixed-Signal Verification | AMS Co-Simulation | SystemVerilog | UVM | Verilog-AMS | RNM | Cadence Xcelium | Virtuoso | Spectre | Behavioral Modeling | Model vs Schematic Verification | Python | Perl | TCL