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Senior Design Verification Engineer – UVM / SystemVerilog
Industry: Semiconductor
Location: Bengaluru
Work Mode: Work from Office
Experience: 8–10 Years
Employment Type: Full-Time
Salary: As per Company Standards
We are looking for experienced Design Verification Engineers with strong hands-on expertise in UVM and SystemVerilog to join our semiconductor engineering team.
8–10 years of experience in Design Verification / ASIC Verification / SoC Verification
Very strong hands-on experience with UVM
Very strong hands-on experience with SystemVerilog
Experience developing and debugging UVM-based verification environments
Strong knowledge of testbenches, sequences, drivers, monitors, scoreboards, assertions, constrained random verification, and functional coverage
Experience with simulation, debugging, regression testing, and coverage closure
Strong problem-solving skills
Exposure to Networking / Networking Protocols
Experience with protocols such as Ethernet, TCP/IP, PCIe, AXI, or similar
Experience in ASIC/SoC/IP verification
Experience with standard EDA simulation/debug tools
Must be willing to work from the office in Bengaluru
Must have 8–10 years of relevant Design Verification experience
UVM and SystemVerilog are mandatory
Key Skills: UVM, SystemVerilog, Design Verification, ASIC Verification, SoC Verification, Functional Verification, Testbench Development, Coverage, Assertions, Networking
Required
Preferred