Senior DFT Engineer – ATPG / SoC & Block Level

Location: Bengaluru
Experience: 5–10 Years
Employment Type: Full-Time
Work Mode: Onsite / Work From Office

Budget: ₹24–35 LPA

Role Overview

We are looking for a Senior DFT Engineer with 5–10 years of relevant experience and strong hands-on expertise in ATPG at SoC level or Block level.

Key Responsibilities

· Develop and execute DFT and ATPG methodologies for complex SoC/block designs.

· Work on SoC-level or Block-level ATPG flows.

· Generate, analyze and debug ATPG patterns.

· Analyze test coverage, fault reports and pattern-related issues.

· Debug ATPG failures and improve test coverage.

· Work closely with RTL, Design, Verification and Physical Design teams.

· Support DFT implementation, verification and sign-off activities.

· Analyze and resolve DFT/ATPG issues across design stages.

Mandatory Requirements

· 5–10 years of relevant DFT experience

· SoC-Level ATPG OR Block-Level ATPG – Mandatory

· Strong hands-on experience in ATPG.

· Strong understanding of DFT concepts and ATPG methodologies.

· Experience in ATPG pattern generation, coverage analysis and debug.

· Candidates must have direct hands-on experience with SoC-level or Block-level ATPG.

Good to Have

· SSN experience

· EDT experience

· Scan compression

· MBIST

· Scan insertion

· DFT verification

· Experience with industry-standard DFT/ATPG tools.

Location

Bengaluru

Key Responsibilities

· Develop and execute DFT and ATPG methodologies for complex SoC/block designs.

· Work on SoC-level or Block-level ATPG flows.

· Generate, analyze and debug ATPG patterns.

· Analyze test coverage, fault reports and pattern-related issues.

· Debug ATPG failures and improve test coverage.

· Work closely with RTL, Design, Verification and Physical Design teams.

· Support DFT implementation, verification and sign-off activities.

· Analyze and resolve DFT/ATPG issues across design stages.

Mandatory Requirements

· 5–10 years of relevant DFT experience

· SoC-Level ATPG OR Block-Level ATPG – Mandatory

· Strong hands-on experience in ATPG.

· Strong understanding of DFT concepts and ATPG methodologies.

· Experience in ATPG pattern generation, coverage analysis and debug.

· Candidates must have direct hands-on experience with SoC-level or Block-level ATPG.

Senior DFT Engineer – ATPG / SoC & Block Level

Apply for this position

Pre-interview questions

Role Overview

Key Responsibilities

Mandatory Requirements

Good to Have

Location

Senior DFT Engineer – ATPG / SoC & Block Level

Apply for this position

Pre-interview questions

Role Overview

Key Responsibilities

Mandatory Requirements

Good to Have

Location