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TalynceTalynce
Find JobsFor CandidatesCandidate PortalContact
TalynceTalynce

AI-powered recruitment automation for modern hiring teams.

Product

  • For Employers
  • For Candidates
  • Features
  • Pricing
  • API Docs

Company

  • About
  • Blog
  • Research
  • Jobs
  • Careers
  • Contact

Legal

  • Privacy Policy
  • Terms of Service
  • Cookie Policy
  • Cancellation & Refund
  • Subscription Changes

© 2026 Talynce AI. All rights reserved.

Talynce.com is a product of Cosette Network.

Back to all jobs
Blueberry Semiconductor

Senior DFT Engineer – ATPG / SoC & Block Level

Bangaloreonsite5.0 - 10.0 years₹24.00L - ₹35.00L

Apply for this position

All fields marked * are required

Actively hiring

Name & contact details are extracted from your resume automatically.

Pre-interview questions

7 required · complete before you apply

1

Years of experience with ATPG?*

Enter a number

2

Current location?*

Short answer

3

Are you open to relocation [Bengaluru]?*

Select one option

4

Work mode preference?*

Select one option

5

Do you have DFT certification?*

Select one option

6

Offers in Hand [If Yes mention CTC Offered]*

Short answer

7

Submitted By: Recruiter or Self*

Short answer

By applying you agree to our Privacy Policy & Terms

Job Description

Senior DFT Engineer – ATPG / SoC & Block Level

Location: Bengaluru
Experience: 5–10 Years
Employment Type: Full-Time
Work Mode: Onsite / Work From Office

Budget: ₹24–35 LPA

Role Overview

We are looking for a Senior DFT Engineer with 5–10 years of relevant experience and strong hands-on expertise in ATPG at SoC level or Block level.

Key Responsibilities

·       Develop and execute DFT and ATPG methodologies for complex SoC/block designs.

·       Work on SoC-level or Block-level ATPG flows.

·       Generate, analyze and debug ATPG patterns.

·       Analyze test coverage, fault reports and pattern-related issues.

·       Debug ATPG failures and improve test coverage.

·       Work closely with RTL, Design, Verification and Physical Design teams.

·       Support DFT implementation, verification and sign-off activities.

·       Analyze and resolve DFT/ATPG issues across design stages.

Mandatory Requirements

·       5–10 years of relevant DFT experience

·       SoC-Level ATPG OR Block-Level ATPG – Mandatory

·       Strong hands-on experience in ATPG.

·       Strong understanding of DFT concepts and ATPG methodologies.

·       Experience in ATPG pattern generation, coverage analysis and debug.

·       Candidates must have direct hands-on experience with SoC-level or Block-level ATPG.

Good to Have

·       SSN experience

·       EDT experience

·       Scan compression

·       MBIST

·       Scan insertion

·       DFT verification

·       Experience with industry-standard DFT/ATPG tools.

Location

Bengaluru

Skills

Required

atpgsocblock

Preferred

ssnedtscan compressionmbistscan insertiondft verification
Back to all jobs
Blueberry Semiconductor

Senior DFT Engineer – ATPG / SoC & Block Level

Bangaloreonsite5.0 - 10.0 years₹24.00L - ₹35.00L

Apply for this position

All fields marked * are required

Actively hiring

Name & contact details are extracted from your resume automatically.

Pre-interview questions

7 required · complete before you apply

1

Years of experience with ATPG?*

Enter a number

2

Current location?*

Short answer

3

Are you open to relocation [Bengaluru]?*

Select one option

4

Work mode preference?*

Select one option

5

Do you have DFT certification?*

Select one option

6

Offers in Hand [If Yes mention CTC Offered]*

Short answer

7

Submitted By: Recruiter or Self*

Short answer

By applying you agree to our Privacy Policy & Terms

Job Description

Senior DFT Engineer – ATPG / SoC & Block Level

Location: Bengaluru
Experience: 5–10 Years
Employment Type: Full-Time
Work Mode: Onsite / Work From Office

Budget: ₹24–35 LPA

Role Overview

We are looking for a Senior DFT Engineer with 5–10 years of relevant experience and strong hands-on expertise in ATPG at SoC level or Block level.

Key Responsibilities

·       Develop and execute DFT and ATPG methodologies for complex SoC/block designs.

·       Work on SoC-level or Block-level ATPG flows.

·       Generate, analyze and debug ATPG patterns.

·       Analyze test coverage, fault reports and pattern-related issues.

·       Debug ATPG failures and improve test coverage.

·       Work closely with RTL, Design, Verification and Physical Design teams.

·       Support DFT implementation, verification and sign-off activities.

·       Analyze and resolve DFT/ATPG issues across design stages.

Mandatory Requirements

·       5–10 years of relevant DFT experience

·       SoC-Level ATPG OR Block-Level ATPG – Mandatory

·       Strong hands-on experience in ATPG.

·       Strong understanding of DFT concepts and ATPG methodologies.

·       Experience in ATPG pattern generation, coverage analysis and debug.

·       Candidates must have direct hands-on experience with SoC-level or Block-level ATPG.

Good to Have

·       SSN experience

·       EDT experience

·       Scan compression

·       MBIST

·       Scan insertion

·       DFT verification

·       Experience with industry-standard DFT/ATPG tools.

Location

Bengaluru

Skills

Required

atpgsocblock

Preferred

ssnedtscan compressionmbistscan insertiondft verification